HD6433644R datasheet(165/549 Pages) RENESAS

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Section 6 ROM

Rev. 6.00 Sep 12, 2006 page 145 of 526

REJ09B0326-0600

.DATA.W

H'2000

; LB1

.DATA.W

H'4000

; LB2

.DATA.W

H'6000

; LB3

.DATA.W

H'8000

; FLASH END

EOWARI:

;

End of erase

ABEND2:

;

Erase error

Loop Counter and Watchdog Timer Overflow Interval Settings in Programs: The settings of

#a, #b, #c, #d, and #e in the program examples depend on the clock frequency. Sample loop

counter settings for typical operating frequencies are shown in table 6.11. The value of #e should

be set as indicated in table 6.12.

As software loops are used, there is intrinsic error, and the calculated value and actual time may

not be the same. Therefore, initial values should be set so that the total write time does not exceed

1 ms, and the total erase time does not exceed 30 s.

The maximum number of writes in the program examples is set as N = 6.

Write and erase operations as shown in the flowcharts are achieved by setting the values of #a, #b,

#c, and #d in the program examples as indicated in table 6.11. Use the settings shown in table 6.12

for the value of #e.

In these sample programs, wait state insertion is disabled. If wait states are used, the setting should

be made after the end of the program.

The set value for the watchdog timer (WDT) overflow time is calculated on the basis of the

number of instructions including the write time and erase time from the time the watchdog timer is

started until it stops. Therefore, no other instructions should be added between starting and

stopping of the watchdog timer in these programs.

HD6433644R Datasheet(PDF) 165 Page - Renesas Technology Corp