HD6433644R datasheet(169/549 Pages) RENESAS

169 / 549 page

Section 6 ROM

Rev. 6.00 Sep 12, 2006 page 149 of 526

REJ09B0326-0600

Hardware Protection: Hardware protection refers to a state in which programming/erasing of

flash memory is forcibly suspended or disabled. At this time, the flash memory control register

(FLMCR) and erase block register (EBR1 and EBR2) settings are cleared.

Details of the hardware protection states are given below.

Functions

Item

Description

Program

Erase

Verify*

Programming

voltage (FVPP)

protect

When 12 V is not being applied to the

FVPP pin, FLMCR, EBR1, and EBR2

are initialized, and the program/erase-

protected state is entered. To obtain

this protection, the VPP voltage should

not exceed the VCC power supply

voltage.*

Disabled

Disabled*

Disabled

Reset/standby

protect

In a reset, (including a watchdog timer

reset), and in sleep, subsleep, watch,

and standby mode, FLMCR, EBR1,

and EBR2 are initialized, and the

program/erase-protected state is

entered. In a reset via the

RES pin, the

reset state is not reliably entered

unless the

RES pin is held low for at

least 20 ms (oscillation settling time)*

after powering on. In the case of a

reset during operation, the

RES pin

must be held low for a minimum of 10

system clock cycles (10

φ).

Disabled

Disabled*

Disabled

Notes: 1. Three modes: program-verify, erase-verify, and prewrite-verify.

2. All blocks are erase-disabled, and individual block specification is not possible.

3. For details, see section 6.9, Flash Memory Programming and Erasing Precautions.

4. For details, see AC Characteristics in section 13, Electrical Characteristics.

6.7.9

Interrupt Handling during Flash Memory Programming/Erasing

If an interrupt is generated while the flash memory is being programmed or erased (while the P or

E bit is set in FLMCR), an operating state may be entered in which the vector will not be read

correctly in the exception handling sequence, resulting in program runaway. All interrupt sources

should therefore be masked to prevent interrupt generation while programming or erasing the flash

memory.

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