HD6433644R datasheet(261/549 Pages) RENESAS

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Section 9 Timers

Rev. 6.00 Sep 12, 2006 page 241 of 526

REJ09B0326-0600

Table 9.15 shows the register configuration of timer X.

Table 9.15 Timer X Registers

Name

Abbr.

R/W

Initial Value

Address

Timer interrupt enable register

TIER

R/W

H'01

H'F770

Timer control/status register X

TCSRX

R/(W)*

H'00

H'F771

Free-running counter H

FRCH

R/W

H'00

H'F772

Free-running counter L

FRCL

R/W

H'00

H'F773

Output compare register AH

OCRAH

R/W

H'FF

H'F774*

Output compare register AL

OCRAL

R/W

H'FF

H'F775*

Output compare register BH

OCRBH

R/W

H'FF

H'F774*

Output compare register BL

OCRBL

R/W

H'FF

H'F775*

Timer control register X

TCRX

R/W

H'00

H'F776

Timer output compare control

TOCR

R/W

H'E0

H'F777

Input capture register AH

ICRAH

H'00

H'F778

Input capture register AL

ICRAL

H'00

H'F779

Input capture register BH

ICRBH

H'00

H'F77A

Input capture register BL

ICRBL

H'00

H'F77B

Input capture register CH

ICRCH

H'00

H'F77C

Input capture register CL

ICRCL

H'00

H'F77D

Input capture register DH

ICRDH

H'00

H'F77E

Input capture register DL

ICRDL

H'00

H'F77F

Notes: 1. Bits 7 to 1 can only be written with 0 for flag clearing. Bit 0 is a read/write bit.

2. OCRA and OCRB share the same address. They are selected by the OCRS bit in

TOCR.

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