HD6433644R datasheet(263/549 Pages) RENESAS

263 / 549 page

Section 9 Timers

Rev. 6.00 Sep 12, 2006 page 243 of 526

REJ09B0326-0600

There are two 16-bit read/write output compare registers, OCRA and OCRB, the contents of

which are always compared with FRC. When the values match, OCFA or OCFB is set to 1 in

TCSRX. If OCIAE = 1 or OCIBE = 1 in TIER, a CPU interrupt is requested.

When a compare match with OCRA or OCRB occurs, if OEA = 1 or OEB = 1 in TOCR, the value

selected by OLVLA or OLVLB in TOCR is output at the FTOA or FTOB pin. After a reset, the

output from the FTOA or FTOB pin is 0 until the first compare match occurs.

OCRA and OCRB can be written and read by the CPU. Since they are 16-bit registers, data is

transferred between them and the CPU via a temporary register (TEMP). For details see section

9.5.3, CPU Interface.

OCRA and OCRB are initialized to H'FFFF upon reset and in standby mode, watch mode,

subsleep mode, and subactive mode.

Input Capture Registers A to D (ICRA to ICRD)

Input Capture Registers AH to DH (ICRAH to ICRDH)

Input Capture Registers AL to DL (ICRAL to ICRDL)

ICRA, ICRB, ICRC, ICRD

Bit

Initial value

Read/Write

ICRAH, ICRBH, ICRCH, ICRDH

ICRAL, ICRBL, ICRCL, ICRDL

There are four 16-bit read only input capture registers, ICRA to ICRD.

When the falling edge of an input capture signal is input, the FRC value is transferred to the

corresponding input capture register, and the corresponding input capture flag (ICFA to ICFD) is

set to 1 in TCSRX. If the corresponding input capture interrupt enable bit (ICIAE to ICIDE) is 1 in

TCRX, a CPU interrupt is requested. The valid edge of the input signal can be selected by bits

IEDGA to IEDGD in TCRX.

ICRC and ICRD can also be used as buffer registers for ICRA and ICRB. Buffering is enabled by

bits BUFEA and BUFEB in TCRX.

Figure 9.17 shows the interconnections when ICRC operates as a buffer register of ICRA (when

BUFEA = 1). When ICRC is used as the ICRA buffer, both the rising and falling edges of the

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