HD6433644R datasheet(271/549 Pages) RENESAS

271 / 549 page

Section 9 Timers

Rev. 6.00 Sep 12, 2006 page 251 of 526

REJ09B0326-0600

Bit 4



 Input Edge Select D (IEDGD): Bit 4 selects the rising or falling edge of the input

capture D input signal (FTID).

Bit 4: IEDGD

Description

Falling edge of input capture D is captured

(initial value)

Rising edge of input capture D is captured

Bit 3



Buffer Enable A (BUFEA): Bit 3 selects whether or not to use ICRC as a buffer register

for ICRA.

Bit 3: BUFEA

Description

ICRC is not used as a buffer register for ICRA

(initial value)

ICRC is used as a buffer register for ICRA

Bit 2



Buffer Enable B (BUFEB): Bit 2 selects whether or not to use ICRD as a buffer register

for ICRB.

Bit 2: BUFEB

Description

ICRD is not used as a buffer register for ICRB

(initial value)

ICRD is used as a buffer register for ICRB

Bits 1 and 0



Clock Select (CKS1, CKS0): Bits 1 and 0 select one of three internal clock

sources or an external clock for input to FRC. The external clock is counted on the rising edge.

Bit 1: CKS1

Bit 0: CKS0

Description

Internal clock:

φ/2

(initial value)

Internal clock:

φ/8

Internal clock:

φ/32

External clock: rising edge

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