HD6433644R datasheet(272/549 Pages) RENESAS

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Section 9 Timers

Rev. 6.00 Sep 12, 2006 page 252 of 526

REJ09B0326-0600

Timer Output Compare Control Register (TOCR)

Bit



OCRS

OEA

OEB

OLVLA

OLVLB

Initial value

Read/Write



R/W

TOCR is an 8-bit read/write register that selects the output compare output levels, enables output

compare output, and controls access to OCRA and OCRB.

TOCR is initialized to H'E0 upon reset and in standby mode, watch mode, subsleep mode, and

subactive mode.

Bits 7 to 5



Reserved Bits: Bit 7 to 5 are reserved; they are always read as 1, and cannot be

modified.

Bit 4



Output Compare Register Select (OCRS): OCRA and OCRB share the same address.

OCRS selects which register is accessed when this address is written or read. It does not affect the

operation of OCRA and OCRB.

Bit 4: OCRS

Description

OCRA is selected

(initial value)

OCRB is selected

Bit 3



Output Enable A (OEA): Bit 3 enables or disables the timer output controlled by output

compare A.

Bit 3: OEA

Description

Output compare A output is disabled

(initial value)

Output compare A output is enabled

Bit 2



Output Enable B (OEB): Bit 2 enables or disables the timer output controlled by output

compare B.

Bit 2: OEB

Description

Output compare B output is disabled

(initial value)

Output compare B output is enabled

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