HD6433644R datasheet(276/549 Pages) RENESAS

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Section 9 Timers

Rev. 6.00 Sep 12, 2006 page 256 of 526

REJ09B0326-0600

9.5.4

Timer Operation

Timer X Operation

• Output compare operation

Following a reset, FRC is initialized to H'0000 and starts counting up. Bits CKS1 and CKS0 in

TCRX can select one of three internal clock sources or an external clock for input to FRC. The

FRC contents are compared constantly with OCRA and OCRB. When a match occurs, the

output at pin FTOA or FTOB goes to the level selected by OLVLA or OLVLB in TOCR.

Following a reset, the output at both FTOA and FTOB is 0 until the first compare match. If

CCLRA is set to 1 in TCSRX, compare match A clears FRC to H'0000.

• Input capture operation

Following a reset, FRC is initialized to H'0000 and starts counting up. Bits CKS1 and CKS0 in

TCRX can select one of three internal clock sources or an external clock for input to FRC.

When the edges selected by bits IEDGA to IEDGD in TCRX are input at pins FTIA to FTID,

the FRC value is transferred to ICRA to ICRD, and ICFA to ICFD are set to 1 in TCSRX. If

bits ICIAE to ICIDE are set to 1 in TIER, a CPU interrupt is requested.

If bits BUFEA and BUFEB are set to 1 in TCRX, ICRC and ICRD operate as buffer registers

for ICRA or ICRB. When the edges selected by bits IEDGA to IEDGD in TCRX are input at

pins FTIA and FTIB, the FRC value is transferred to ICRA or ICRB, and the previous value in

ICRA or ICRB is transferred to ICRC or ICRD. Simultaneously, ICFA or ICFB is set to 1. If

bit ICIAE or ICIBE is set to 1 in TIER, a CPU interrupt is requested.

HD6433644R Datasheet(PDF) 276 Page - Renesas Technology Corp