 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
HD6433644R Datasheet(PDF) 279 Page - Renesas Technology Corp |
|
|
|||||||||||||||||||||||||||||
HD6433644R Datasheet(HTML) 279 Page - Renesas Technology Corp |
|
|
279 / 549 page  Section 9 Timers Rev. 6.00 Sep 12, 2006 page 259 of 526 REJ09B0326-0600 Input Capture Timing • Input capture timing The rising or falling edge is selected for input capture by bits IEDGA to IEDGD in TCRX. Figure 9.24 shows the timing when the rising edge is selected (IEDGA/B/C/D = 1). Input capture signal φ Input capture pin Figure 9.24 Input Capture Signal Timing (Normal Case) If the input at the input capture pin occurs while the upper byte of the corresponding input capture register (ICRA to ICRD) is being read, the internal input capture signal is delayed by one system clock ( φ). Figure 9.25 shows the timing. Input capture signal φ Input capture pin T1 T2 T3 ICRA to ICRD upper byte read cycle Figure 9.25 Input Capture Signal Timing (during ICRA to ICRD Read) |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
