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HD6433644R Datasheet(PDF) 281 Page - Renesas Technology Corp |
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HD6433644R Datasheet(HTML) 281 Page - Renesas Technology Corp |
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281 / 549 page ![]() Section 9 Timers Rev. 6.00 Sep 12, 2006 page 261 of 526 REJ09B0326-0600 Input capture signal φ FTIA T1 T2 T3 ICRA or ICRC upper byte read cycle by CPU Figure 9.27 Buffered Input Capture Signal Timing (during ICRA or ICRD Read) Input Capture Flag (ICFA to ICFD) Set Timing: Figure 9.28 shows the timing when an input capture flag (ICFA to ICFD) is set to 1 and the FRC value is transferred to the corresponding input capture register (ICRA to ICRD). ICFA to ICFD φ FRC Input capture signal N N ICRA to ICRD Figure 9.28 ICFA to ICFD Set Timing |
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