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HD6433644R Datasheet(PDF) 285 Page - Renesas Technology Corp |
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HD6433644R Datasheet(HTML) 285 Page - Renesas Technology Corp |
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285 / 549 page ![]() Section 9 Timers Rev. 6.00 Sep 12, 2006 page 265 of 526 REJ09B0326-0600 9.5.8 Application Notes The following types of contention can occur in timer X operation. 1. Contention between FRC write and counter clear If an FRC clear signal is generated in the T3 state of a write cycle to the lower byte of FRC, clearing takes precedence and the write to the counter is not carried out. Figure 9.32 shows the timing. T1 T2 T3 FRC lower byte write cycle Address FRC address Internal write signal φ Counter clear signal FRC N H'0000 Figure 9.32 Contention between FRC Write and Clear |
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