HD6433644R datasheet(288/549 Pages) RENESAS

288 / 549 page

Section 9 Timers

Rev. 6.00 Sep 12, 2006 page 268 of 526

REJ09B0326-0600

4. Internal clock switching and counter operation

Depending on the timing, FRC may be incremented by a switch between different internal

clock sources. Table 9.19 shows the relation between internal clock switchover timing (by

writing to bits CKS1 and CKS0) and FRC operation.

When FRC is internally clocked, an increment pulse is generated from the falling edge of an

internal clock signal, which is divided from the system clock (

φ). For this reason, in a case like

No. 3 in table 9.19 where the switch is from a high clock signal to a low clock signal, the

switchover is seen as a falling edge, causing FRC to increment.

FRC can also be incremented by a switch between internal and external clocks.

Table 9.19 Internal Clock Switching and FRC Operation

No.

Clock Levels Before

and After Modifying

Bits CKS1 and CKS0

FRC Operation

Goes from low level

to low level

N + 1

Clock before

switching

Clock after

switching

Count clock

FRC

Write to CKS1 and CKS0

Goes from low

to high

N + 1

N + 2

Clock before

switching

Clock after

switching

Count clock

FRC

Write to CKS1 and CKS0

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