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HD6433644R Datasheet(PDF) 287 Page - Renesas Technology Corp |
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HD6433644R Datasheet(HTML) 287 Page - Renesas Technology Corp |
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287 / 549 page ![]() Section 9 Timers Rev. 6.00 Sep 12, 2006 page 267 of 526 REJ09B0326-0600 3. Contention between OCR write and compare match If a compare match is generated in the T3 state of a write cycle to the lower byte of OCRA or OCRB, the write to OCRA or OCRB takes precedence and the compare match signal is inhibited. Figure 9.34 shows the timing. T1 T2 T3 OCR lower byte write cycle Address Internal write signal φ FRC OCR N M Write data OCR address N N + 1 Compare match signal Inhibited Figure 9.34 Contention between OCR Write and Compare Match |
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