HD6433644R datasheet(291/549 Pages) RENESAS

291 / 549 page

Section 9 Timers

Rev. 6.00 Sep 12, 2006 page 271 of 526

REJ09B0326-0600

Table 9.20 shows the register configuration of the watchdog timer.

Table 9.20

Watchdog Timer Registers

Name

Abbr.

R/W

Initial Value

Address

Timer control/status register W

TCSRW

R/W

H'AA

H'FFBE

Timer counter W

TCW

R/W

H'00

H'FFBF

9.6.2

Timer Control/Status Register W (TCSRW)

Bit

B6WI

TCWE

B4WI

TCSRWE B2WI

WDON

B0WI

WRST

Initial value

Read/Write

R/(W)*

Note:

* Write is permitted only under certain conditions, which are given in the descriptions of

the individual bits.

TCSRW is an 8-bit read/write register that controls write access to TCW and TCSRW itself,

controls watchdog timer operations, and indicates operating status.

Bit 7



Bit 6 Write Inhibit (B6WI): Bit 7 controls the writing of data to bit 6 in TCSRW.

This bit is always read as 1. Data written to this bit is not stored.

Bit 7: B6WI

Description

Bit 6 is write-enabled

Bit 6 is write-protected

(initial value)

Bit 6



Timer Counter W Write Enable (TCWE): Bit 6 controls the writing of data to bit 8 to

TCW.

Bit 6: TCWE

Description

Data cannot be written to TCW

(initial value)

Data can be written to TCW

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