HD6433644R datasheet(293/549 Pages) RENESAS

293 / 549 page

Section 9 Timers

Rev. 6.00 Sep 12, 2006 page 273 of 526

REJ09B0326-0600

Bit 1



Bit 0 Write Inhibit (B0WI): Bit 1 controls the writing of data to bit 0 in TCSRW.

This bit is always read as 1. Data written to this bit is not stored.

Bit 1: B0WI

Description

Bit 0 is write-enabled

Bit 0 is write-protected

(initial value)

Bit 0



Watchdog Timer Reset (WRST): Bit 0 indicates that TCW has overflowed, generating

an internal reset signal. The internal reset signal generated by the overflow resets the entire chip.

WRST is cleared to 0 by a reset from the

RES pin, or when software writes 0.

Bit 0: WRST

Description

Clearing conditions:

(initial value)

• Reset by RES pin

• When TCSRWE = 1, and 0 is written in both B0WI and WRST

Setting condition:

When TCW overflows and an internal reset signal is generated

Timer Counter W (TCW)

Bit

TCW7

TCW6

TCW5

TCW4

TCW3

TCW2

TCW1

TCW0

Initial value

Read/Write

R/W

TCW is an 8-bit read/write up-counter, which is incremented by internal clock input. The input

clock is

φ/8192. The TCW value can always be written or read by the CPU.

When TCW overflows from H'FF to H'00, an internal reset signal is generated and WRST is set to

1 in TCSRW. Upon reset, TCW is initialized to H'00.

HD6433644R Datasheet(PDF) 293 Page - Renesas Technology Corp

HD6433644R Datasheet(HTML) 293 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL