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HD6433644R Datasheet(PDF) 290 Page - Renesas Technology Corp |
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HD6433644R Datasheet(HTML) 290 Page - Renesas Technology Corp |
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290 / 549 page  Section 9 Timers Rev. 6.00 Sep 12, 2006 page 270 of 526 REJ09B0326-0600 9.6 Watchdog Timer 9.6.1 Overview The watchdog timer has an 8-bit counter that is incremented by an input clock. If a system runaway allows the counter value to overflow before being rewritten, the watchdog timer can reset the chip internally. Features Features of the watchdog timer are given below. • Incremented by internal clock source (φ/8192). • A reset signal is generated when the counter overflows. The overflow period can be set from 1 to 256 times 8192/ φ (from approximately 2 ms to 500 ms when φ = 4.19 MHz). Block Diagram Figure 9.35 shows a block diagram of the watchdog timer. PSS TCSRW TCW φ/8192 Legend: TCSRW: TCW: PSS: Timer control/status register W Timer counter W Prescaler S φ Internal reset signal Figure 9.35 Block Diagram of Watchdog Timer |
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