HD6433644R datasheet(294/549 Pages) RENESAS

294 / 549 page

Section 9 Timers

Rev. 6.00 Sep 12, 2006 page 274 of 526

REJ09B0326-0600

9.6.3

Timer Operation

The watchdog timer has an 8-bit counter (TCW) that is incremented by clock input (

φ/8192).

When TCSRWE = 1 in TCSRW, if 0 is written in B2WI and 1 is simultaneously written in

WDON, TCW starts counting up (two write accesses to TCSRW are necessary in order to operate

the watchdog timer). When the TCW count value reaches H'FF, the next clock input causes the

watchdog timer to overflow and generates an internal reset signal. The internal reset signal is

output for 512 clock cycles of the

φOSC clock. It is possible to write to TCW, causing TCW to

count up from the written value. The overflow period can be set in the range from 1 to 256 input

clocks, depending on the value written in TCW.

Figure 9.36 shows an example of watchdog timer operations.

Example:

φ = 4 MHz and the desired overflow period is 30 ms.

× 106

8192

× 30 × 10–3 = 14.6

The value set in TCW should therefore be 256 – 15 = 241 (H'F1).

H'F1

TCW overflow

Start

H'F1 written

in TCW

H'F1 written in TCW

Reset

Internal reset

signal

512

OSC clock cycles

H'FF

H'00

TCW count

value

Figure 9.36 Typical Watchdog Timer Operations (Example)

HD6433644R Datasheet(PDF) 294 Page - Renesas Technology Corp