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HD6433644R Datasheet(PDF) 298 Page - Renesas Technology Corp |
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HD6433644R Datasheet(HTML) 298 Page - Renesas Technology Corp |
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298 / 549 page  Section 10 Serial Communication Interface Rev. 6.00 Sep 12, 2006 page 278 of 526 REJ09B0326-0600 Features • Choice of 8-bit or 16-bit data length • Choice of eight internal clock sources (φ/1024, φ/256, φ/64, φ/32, φ/16, φ/8, φ/4, φ/2) or an external clock • Interrupt requested at completion of transfer • Choice of HOLD mode or LATCH mode in SSB mode. Block Diagram Figure 10.1 shows a block diagram of SCI1. φ SCK1 SI1 SO1 SCR1 SCSR1 SDRU SDRL PSS Transfer bit counter Transmit/receive control circuit Legend: SCR1: SCSR1: SDRU: SDRL: IRRS1: PSS: Serial control register 1 Serial control/status register 1 Serial data register U Serial data register L SCI1 interrupt request flag Prescaler S IRRS1 Figure 10.1 SCI1 Block Diagram |
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