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HD6433644R Datasheet(PDF) 314 Page - Renesas Technology Corp |
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HD6433644R Datasheet(HTML) 314 Page - Renesas Technology Corp |
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314 / 549 page ![]() Section 10 Serial Communication Interface Rev. 6.00 Sep 12, 2006 page 294 of 526 REJ09B0326-0600 Transmit Data Register (TDR) Bit 7 6 5 4 3 2 1 0 TDR7 TDR6 TDR5 TDR4 TDR3 TDR2 TDR1 TDR0 Initial value 1 1 1 1 1 1 1 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W TDR is an 8-bit register that stores transmit data. When TSR is found to be empty, the transmit data written in TDR is transferred to TSR, and serial data transmission is started. Continuous transmission is possible by writing the next transmit data to TDR during TSR serial data transmission. TDR can be read or written by the CPU at any time. TDR is initialized to H'FF upon reset, and in standby, watch, subactive, or subsleep mode. Serial Mode Register (SMR) Bit 7 6 5 4 3 2 1 0 COM CHR PE PM STOP MP CKS1 CKS0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W SMR is an 8-bit register used to set the serial data transfer format and to select the clock source for the baud rate generator. SMR can be read or written by the CPU at any time. SMR is initialized to H'00 upon reset, and in standby, watch, subactive, or subsleep mode. Bit 7 Communication Mode (COM): Bit 7 selects whether SCI3 operates in asynchronous mode or synchronous mode. Bit 7: COM Description 0 Asynchronous mode (initial value) 1 Synchronous mode |
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