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HD6433644R Datasheet(PDF) 326 Page - Renesas Technology Corp |
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HD6433644R Datasheet(HTML) 326 Page - Renesas Technology Corp |
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326 / 549 page ![]() Section 10 Serial Communication Interface Rev. 6.00 Sep 12, 2006 page 306 of 526 REJ09B0326-0600 Notes: 1. The setting should be made so that the error is not more than 1%. 2. The value set in BRR is given by the following equation: N = × 106 – 1 OSC (64 × 22n × B) where B: Bit rate (bit/s) N: Baud rate generator BRR setting (0 ≤ N ≤ 255) OSC: Value of φOSC (MHz) n: Baud rate generator input clock number (n = 0, 1, 2, or 3) (The relation between n and the clock is shown in table 10.7.) Table 10.7 Relation between n and Clock SMR Setting n Clock CKS1 CKS0 0 φ 0 0 1 φ/4 0 1 2 φ16 1 0 3 φ/64 1 1 3. The error in table 10.6 is the value obtained from the following equation, rounded to two decimal places. B (rate obtained from n, N, OSC) – R (bit rate in left-hand column in table 10.6) R (bit rate in left-hand column in table 10.6) Error (%) = × 100 |
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