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HD6433644R Datasheet(PDF) 324 Page - Renesas Technology Corp |
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HD6433644R Datasheet(HTML) 324 Page - Renesas Technology Corp |
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324 / 549 page ![]() Section 10 Serial Communication Interface Rev. 6.00 Sep 12, 2006 page 304 of 526 REJ09B0326-0600 Bit Rate Register (BRR) Bit 7 6 5 4 3 2 1 0 BRR7 BRR6 BRR5 BRR4 BRR3 BRR2 BRR1 BRR0 Initial value 1 1 1 1 1 1 1 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W BRR is an 8-bit register that designates the transmit/receive bit rate in accordance with the baud rate generator operating clock selected by bits CKS1 and CKS0 of the serial mode register (SMR). BRR can be read or written by the CPU at any time. BRR is initialized to H'FF upon reset, and in standby, watch, subactive, or subsleep mode. Table 10.6 shows examples of BRR settings in asynchronous mode. The values shown are for active (high-speed) mode. Table 10.6 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) OSC (MHz) 2 2.4576 4 4.194304 Bit Rate (bits/s) n N Error (%) n N Error (%) n N Error (%) n N Error (%) 110 1 70 +0.03 1 86 +0.31 1 141 +0.03 1 148 –0.04 150 0 207 +0.16 0 255 0 1 103 +0.16 1 108 +0.21 300 0 103 +0.16 0 127 0 0 207 +0.16 0 217 +0.21 600 0 51 +0.16 0 63 0 0 103 +0.16 0 108 +0.21 1200 0 25 +0.16 0 31 0 0 51 +0.16 0 54 –0.70 2400 0 12 +0.16 0 15 0 0 25 +0.16 0 26 +1.14 4800 0 7 0 0 12 +0.16 0 13 –2.48 9600 0 3 0 0 6 –2.48 19200 0 1 0 31250 0 0 0 0 1 0 38400 0 0 0 |
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