HD6433644R datasheet(320/549 Pages) RENESAS

320 / 549 page

Section 10 Serial Communication Interface

Rev. 6.00 Sep 12, 2006 page 300 of 526

REJ09B0326-0600

Serial Status Register (SSR)

Bit

TDRE

RDRF

OER

FER

PER

TEND

MPBR

MPBT

Initial value

Read/Write

R/(W)*

R/W

Note:

* Only a write of 0 for flag clearing is possible.

SSR is an 8-bit register containing status flags that indicate the operational status of SCI3, and

multiprocessor bits.

SSR can be read or written by the CPU at any time, but only a write of 1 is possible to bits TDRE,

RDRF, OER, PER, and FER. In order to clear these bits by writing 0, 1 must first be read.

Bits TEND and MPBR are read-only bits, and cannot be modified.

SSR is initialized to H'84 upon reset, and in standby, watch, subactive, or subsleep mode.

Bit 7



Transmit Data Register Empty (TDRE): Bit 7 indicates that transmit data has been

transferred from TDR to TSR.

Bit 7: TDRE

Description

Transmit data written in TDR has not been transferred to TSR

Clearing conditions:

• After reading TDRE = 1, cleared by writing 0 to TDRE

• When data is written to TDR by an instruction

Transmit data has not been written to TDR, or transmit data written in TDR has

been transferred to TSR

Setting conditions:

• When bit TE in SCR3 is cleared to 0

• When data is transferred from TDR to TSR

(initial value)

HD6433644R Datasheet(PDF) 320 Page - Renesas Technology Corp