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SH7021 Datasheet(PDF) 152 Page - Renesas Technology Corp |
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SH7021 Datasheet(HTML) 152 Page - Renesas Technology Corp |
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152 / 509 page  134 RENESAS 8.5 DRAM Interface Operation When the DRAM enable bit (DRAME) of the BCR is set to 1, area 1 becomes DRAM space and the DRAM interface function is available, which permits direct connection of this LSI to DRAMs. 8.5.1 DRAM Address Multiplexing When the multiplex enable bit (MXE) of the DRAM area control register (DCR) is set to 1, row addresses and column addresses are multiplexed. This allows DRAMs that require multiplexing of row and column addresses to be connected directly to the SH microprocessors without additional multiplexing circuits. When addresses are multiplexed (MXE = 1), setting of the DCR’s multiplex shift bits (MXC1, MXC0) allows selection of eight, nine and ten-bit row address shifting. Table 8.9 illustrates the relationship between MXC1/MXC0 bits and address multiplexing. |
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