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SH7021 Datasheet(PDF) 150 Page - Renesas Technology Corp |
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SH7021 Datasheet(HTML) 150 Page - Renesas Technology Corp |
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150 / 509 page  132 RENESAS T1 CK A21–A0 CSn RD AD15–AD0 WRH , WRL AD15–AD0 Write WAIT Wait states set in WCR3 Wait state from WAIT signal input Wait states set in WCR3 TLW1 TLW2 TW TLW3 Read Figure 8.14 Wait State Timing for External Memory Space Access (1 state plus long wait state (when set to insert 3 states) plus wait states from WAIT signal) For CPU write cycles and DMAC dual mode write cycles to external memory space, the number of states and wait state insertion cannot be controlled by WCR1. In areas 1, 3, 4, 5, and 7, the WAIT signal is sampled and the number of states is 2 plus the number of wait states in the WAIT signal (figure 8.13). In areas 0, 2 and 6, the number of states is 1 state plus the number of long wait states plus the number of wait states in the WAIT signal (figure 8.14). Never write 0 in bits 7–2 and 0 of WCR1; only write 1. When area 1 is being used as external memory space, never write 0 to bit 1 (WW1); always write 1. |
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