SH7021 datasheet(151/509 Pages) RENESAS

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8.4.3

Byte Access Control

The upper byte and lower byte control signals when 16-bit bus width space is being accessed can

be selected from (

WRH, WRL, A0) or (WR, HBS, LBS). When the byte access select bit (BAS)

of the BCR is set to 1, the

WRH, WRL, and A0 pins output WR, LBS and HBS signals. Figure

8.15 illustrates the control signal output timing in the byte write cycle.

WRH

WRL

HBS

LBS

BAS = 0

BAS = 1

Upper byte access

Lower byte access

Figure 8.15 Byte Access Control Timing For External Memory Space Access (Write Cycle)

The

WRH, WRL system and the HBS, LBS system are available as byte access signals for the 16-

bit space in the address/data multiplexing space and the external memory space.

These strobe signals are assigned to pins in the manner: A0/

HBS, WRH/LBS, WRL/WR, and the

BAS bit of the bus control register (BCR) is used to switch specify signal sending.

Note that the byte access signals are strobe signals dedicated to byte access to a 16-bit space and

not to be used for byte access to an 8-bit space. When making an access to an 8-bit space, use the

A0/

HBS pin as A0 irrespective of the BAS bit value (0 or 1) to use the WRL/WR pin as the WR

pin, and avoid using the

WRH/LBS pin.

SH7021 Datasheet(PDF) 151 Page - Renesas Technology Corp