SH7021 datasheet(175/509 Pages) RENESAS

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For details on bus cycles when external spaces are accessed, see section 8.4, External Memory

Space Access, section 8.5, DRAM Space Access, and section 8.6, Address/Data Multiplexed I/O

Space Access.

Accesses of on-chip spaces are as follows: On-chip peripheral module spaces (area 5 when address

bit A27 is 1) are always 3 states, regardless of the WCR, with no

WAIT signal sampling. Accesses

of on-chip ROM (area 0 when MD2–MD0 are 010) and on-chip RAM (area 7 when address bit

A27 is 0) are always performed in 1 state, regardless of the WCR, with no

WAIT signal sampling.

If the bus timing specifications (tWTS and tWTH) are not observed when the WAIT signal is input

in external space access, this will simply mean that

WAIT signal assertion and negation will not

be detected, but will not result in misoperation. Note, however, that the inability to detect

WAIT

signal assertion may result in a problem with memory access due to insertion of an insufficient

number of waits.

8.10

Bus Arbitration

The SuperH microcomputer can release the bus to external devices when they request the bus. It

has two internal bus masters, the CPU and the DMAC. Priorities for releasing the bus for these

two are as follows.

Bus request from external device > refresh > DMAC > CPU

Thus, an external device has priority when it generates a bus request, even when the DMAC is

doing a burst transfer.

Note that when a refresh request is generated while the bus is released to an external device,

BACK becomes high level and the bus right can be acquired to perform the refresh upon receipt of

BREQ = high level response from the external device. Input all bus requests from external

devices to the

BREQ pin. The signal indicating that the bus has been released is output from the

BACK pin. Figure 8.35 illustrates the bus release procedure.

SH7021 Datasheet(PDF) 175 Page - Renesas Technology Corp