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SH7021 Datasheet(PDF) 176 Page - Renesas Technology Corp

Part # SH7021
Description  SuperH??RISC engine
PDF  509 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7021 Datasheet(HTML) 176 Page - Renesas Technology Corp

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158 RENESAS
Bus released
BREQ received
Bus acquisition
BREQ = low
BACK = low
acknowledge
BACK
Bus request
External device
SuperH
Bus release response
Address, data, strobe pin:
High impedance
Strobe pin:
High-level output
Figure 8.35 Bus Release Procedure
8.10.1
The Operation of Bus Arbitration
This LSI has the bus arbitration function which can give bus ownership to an external device when
the device requests the bus ownership. When
BREQ is input and the bus cycle being executed by
the CPU or DMAC is completed,
BACK becomes low and a bus is released for an external device.
At this time, the following operates when bus arbitration conflicts with refresh.
1. If DRAM refresh is requested in this LSI when a bus is released and
BACK is low, BACK
becomes high and the occurrence of the refresh request can be informed externally. At this
time, the external device may generate a bus cycle when
BREQ is low even if BACK is high.
Therefore, a bus remains released to the external device. Then, when
BREQ becomes high, this
LSI gets bus ownership, and executes refresh and the bus cycle of the CPU or DMAC. After
the external device gets bus ownership and
BACK is low, refresh is requested when BACK
becomes high even if the low level of
BREQ is input. Therefore, turn BREQ high immediately
to release a bus for this LSI to hold DRAM data (See figure 8.36).
2. When
BREQ changes from high to low and internal refresh is requested at the timing of the
bus release of this LSI,
BACK may remain high (do not become low). A bus is released to the
external device since the low level of
BREQ is input. This operation is based on the above
specification (1). To hold DRAM data, turn
BREQ high and release a bus to this LSI
immediately when the external device detects that
BACK does not change to low during a
fixed time this LSI (See figure 8.37). When a refresh request is generated and
BACK returns
to high, as shown in figure 8.37, a momentary narrow pulse-shaped spike may be output where
BACK was originally supposed to become low.



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