SH7021 datasheet(178/509 Pages) RENESAS

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2. Countermeasure against a spike on the

BACK signal

The following describes the countermeasure against a spike on the

BACK signal:

a. When

BREQ is input to release the bus of the LSI, make sure that conflicts with a refresh

operation do not occur. Stop the refresh operation or operate the refresh timer counter

(RTCNT) or the refresh time constant register (RTCOR) of the bus controller (BSC) to

shift the refresh timing.

b. The spike on the

BACK signal has a narrow pulse width of approximately 2 to 5 ns, which

can be eliminated by using a capacitor as shown in the figure below.

For example, adding a capacitance of 220 pF can raise the minimum voltage of the spike

above 2.0 V.

Note that delay of the

BACK signal increases approximately in units of 0.1 ns/pF. (When a

capacitance of 220 pF is added, the delay increases approximately by 22 ns.

BACK

SuperH

Microcomputer

Capacitor-incorporating circuit for eliminating a spike

c. Latching the

BACK signal by using a flip-flop or triggering the flip-flop may be successful

or unsuccessful due to the narrow pulse width of the spike. Implement a circuit

configuration which will cause no problems when latching BACK or using

BACK as a

trigger signal.

When splitting the

BACK signal into two signals and latching each of them using the flip-

flop or triggering the flip-flop, the flip-flop may operate for one signal but may not for

another. To capture the BACK signal using the flip-flop, receive the

BACK signal using a

single flip-flop then distribute the signal (see figure below).

SH7021 Datasheet(PDF) 178 Page - Renesas Technology Corp