SH7021 datasheet(174/509 Pages) RENESAS

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156 RENESAS

Table 8.11

Bus Cycle States when Accessing Address Spaces

CPU Read Cycle, DMAC Dual Mode Read Cycle, DMAC Single

Mode Memory Read/Write Cycle

Address Space

Corresponding Bits in WCR1

and WCR2 = 0

Corresponding Bits in WCR1

and WCR2 = 1

External memory (areas

1, 3–5, 7)

1 state fixed; WAIT signal ignored 2 states + wait states from WAIT

signal

External memory (Areas

0, 2, 6; long wait avail-

able)

1 state + long wait state*, WAIT

signal ignored

1 state + long wait state* + wait

states from WAIT signal

DRAM space (area 1)

Column address cycle: 1 state,

WAIT signal ignored (short pitch)

Column address cycle: 2 states +

wait states from WAIT signal

(long pitch)

Multiplexed I/O space

(area 6)

4 states + wait states from WAIT signal

On-chip peripheral mod-

ule space (area 5)

3 states fixed, WAIT signal ignored

On-chip ROM (area 0)

1 state fixed, WAIT signal ignored

On-chip RAM (area 7)

1 state fixed, WAIT signal ignored

CPU Write Cycle, DMAC Dual Mode Memory Write Cycle

Address Space

WW1 of WCR1 = 0

WW1 of WCR1 =1

External memory (areas

1, 3–5, 7)

2 states + wait states from WAIT signal

External memory (Areas

0, 2, 6; long wait

available)

1 state + long wait state* + wait states from WAIT signal

DRAM space (area 1)

Column address cycle: 1 state,

WAIT signal ignored (short pitch)

Column address cycle: 2 states +

wait states from WAIT signal

(long pitch)

Multiplexed I/O space

(area 6)

4 states + wait states from WAIT signal

On-chip peripheral

module space (area 5)

3 states fixed, WAIT signal ignored

On-chip ROM (area 0)

1 state fixed, WAIT signal ignored

On-chip RAM (area 7)

1 state fixed, WAIT signal ignored

Note:

The number of long wait states (1 to 4) is set in WCR3.

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