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SH7021 Datasheet(PDF) 232 Page - Renesas Technology Corp |
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SH7021 Datasheet(HTML) 232 Page - Renesas Technology Corp |
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232 / 509 page ![]() 216 RENESAS 10.1.2 Block Diagram ITU Block Diagram (Complete): Figure 10.1 is the block diagram of the ITU. TOCR TSTR TSNC TMDR TFCR Module data bus Internal data bus Clock selection Counter control and pulse I/O control unit TCLKA–TCLKD φ, φ/2, φ/4, φ/8 TOCXA4, TOCXB4 TIOCA0–TIOCA4 TIOCB0–TIOCB4 IMIA0–IMIA4 IMIB0–IMIB4 OVI0–OVI4 Control logic TOCR: Timer output control register (8 bits) TSTR: Timer start regsiter (8 bits) TSNC: Timer synchronization register (8 bits) TMDR: Timer mode register (8 bits) TFCR: Timer function control register (8 bits) Figure 10.1 ITU Block Diagram |
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