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SH7021 Datasheet(PDF) 228 Page - Renesas Technology Corp |
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SH7021 Datasheet(HTML) 228 Page - Renesas Technology Corp |
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228 / 509 page  RENESAS 211 8. When the following operations are performed in the order shown when the pin to which DREQ input is assigned is designated as a general input pin by the pin function controller (PFC) and inputs a low-level signal, the DREQ falling edge is detected, and a DMA transfer request accepted, immediately after the setting in (b) is performed: (a) A channel control register (CHCRn) setting is made so that an interrupt is detected at the falling edge of DREQ. (b) The function of the pin to which DREQ input is assigned is switched from general input to DREQ input by a pin function controller (PFC) setting. Therefore, when switching the pin function from general input pin to DREQ input, the pin function controller (PFC) setting should be changed to DREQ input while the pin to which DREQ input is assigned is high. |
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