SH7021 datasheet(227/509 Pages) RENESAS

227 / 509 page

210 RENESAS

Number of states of

DMAC bus cycle

: Bus cycle of DMAC

Sampling point

Figure 9.16 Sampling Points of DREQ

Especially as shown in Figure 9.17, if the bus cycle of DMA is a full access to DRAM or if

refresh demand is generated, sampling of

DREQ takes place before DACK is output as

mentioned above. This phenomenon is found when one of the following transfers is made with

DREQ set to the level detection in the DMA cycle steal mode, in a system which employs

DRAM (refresh enabled).

Sampling point

When refresh operation is entered

Sampling point of DREQ for DACK output position

differs with presence/absence of the refresh operation.

Refresh

DACK

Sampling point

Bus cycle of DRAM

(Full access)

Figure 9.17 Example of DREQ Sampling before Output of DACK

• Transfer from a device having DACK to memory in the single address mode (not

restricted to DRAM)

• Transfer from DRAM to a device having DACK in the single address mode

• Output at DACK write in the dual address mode

Output at DACK read in the dual address mode and DMA transfer using DRAM as a

source

•

Countermeasure

To prevent unnecessary DMA transfers, configure the system where

DREQ is used for edge

detection and the edge corresponding to the next transfer request occurs after the DACK

output.

SH7021 Datasheet(PDF) 227 Page - Renesas Technology Corp