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Table 10.14 Output Pins for Complementary PWM Mode

Channel

Output Pin

Description

TIOCA3

PWM output 1

TIOCB3

PWM output 1' (non-overlapping negative-phase waveform of

PWM output 1)

TIOCA4

PWM output 2

TOCXA4

PWM output 2' (non-overlapping negative-phase waveform of

PWM output 2)

TIOCB4

PWM output 3

TOCXB4

PWM output 3' (non-overlapping negative-phase waveform of

PWM output 3)

Table 10.15 Register Settings for Complementary PWM Mode

Description of Contents

TCNT3

Initial setting of non-overlap cycle (the difference with TCNT4)

TCNT4

Initial setting of H'0000

GRA3

Set upper limit of TCNT3–1

GRB3

Sets the turning point for PWM waveform output by the TIOCA3 and TIOCB3 pins.

GRA4

Sets the turning point for PWM waveform output by the TIOCA4 and TOCXA4 pins.

GRB4

Sets the turning point for PWM waveform output by the TIOCB4 and TOCXB4 pins.

Procedure for Selecting the Complementary PWM Mode (figure 10.33):

1. Clear STR3 and STR4 bits in the TSTR to halt the timer counters. The complementary PWM

mode must be set up while TCNT3 and TCNT4 are halted.

2. Set bits TPSC2–TPSC0 in the TCR to select the same counter clock source for channels 3 and

4. If an external clock source is selected, select the external clock edges with bits CKEG1 and

CKEG0 in the TCR. Do not select any counter clear source with bits CCLR1 and CCLR0 in

the TCR.

3. Set bits CMD1 and CMD0 in TMDB to select the complementary PWM mode. TIOCA3–

TIOCB4, TOCXA4, and TOCXB4 automatically become PWM pins.

4. Reset TCNT4 (to H'0000). Set the non-overlap offset in TCNT3. Do not set TCNT3 and

TCNT4 to the same value.

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