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10.4.5

Reset-Synchronized PWM Mode

In the reset-synchronized PWM mode, three pairs of complementary positive and negative PWM

waveforms that share a common wave turning point can be obtained using channels 3 and 4. When

set for reset-synchronized PWM mode, the TIOCA3, TIOCB3, TIOCA4, TOCXA4, TIOCB4, and

TOCXB4 pins automatically become PWM output pins and TCNT3 becomes an upcounter. Table

10.12 shows the PWM output pins used and table 10.13 shows the settings of the registers used.

Table 10.12 Output Pins for Reset-Synchronized PWM Mode

Channel

Output Pin

Description

TIOCA3

PWM output 1

TIOCB3

PWM output 1' (negative-phase waveform of PWM output 1)

TIOCA4

PWM output 2

TOCXA4

PWM output 2' (negative-phase waveform of PWM output 2)

TIOCB4

PWM output 3

TOCXB4

PWM output 3' (negative-phase waveform of PWM output 3)

Table 10.13 Register Settings for Reset-Synchronized PWM Mode

Description of Contents

TCNT3

Initial setting of H'0000

TCNT4

Not used (functions independently)

GRA3

Set count cycle for TCNT3

GRB3

Sets the turning point for PWM waveform output by the TIOCA3 and TIOCB3 pins

GRA4

Sets the turning point for PWM waveform output by the TIOCA4 and TOCXA4 pins

GRB4

Sets the turning point for PWM waveform output by the TIOCB4 and TOCXB4 pins

Procedure for Selecting the Reset-Synchronized PWM Mode (figure 10.31):

1. Clear the STR3 bits in the TSTR to halt TCNT3. The reset-synchronized PWM mode must be

set up while TCNT3 is halted.

2. Set bits TPSC2–TPSC0 in the TCR to select the counter clock source for channel 3. If an

external clock source is selected, select the external clock edges with bits CKEG1 and CKEG0

in the TCR.

3. Set bits CCLR1 and CCLR0 in the TCR3 to select GRA3 as a counter clear source.

4. Set bits CMD1 and CMD0 in TMDB to select the reset-synchronized PWM mode. TIOCA3–

TIOCB4, TOCXA4, and TOCXB4 automatically become PWM output pins.

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