SH7021 datasheet(311/509 Pages) RENESAS

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RENESAS 295

10.6.13

Clearing the Complementary PWM Mode

Figure 10.69 shows the procedure for clearing the complementary PWM mode. First, reset the

combination mode bits CMD1 and CMD0 in the timer function control register (TFCR) from 10 to

either 00 or 01. The mode will switch from complementary PWM mode to normal operating

mode. Next, wait for at least 1 clock of the counter input clock being used for channels 3 and 4

and then clear the counter start bits STR3 and STR4 of the timer start register (TSTR). The

channels 3 and 4 counters TCNT3 and TCNT4 will stop counting. Clearing the complementary

PWM mode by any other procedure may result in changes other than those set for the output

waveform when complementary PWM mode is set again.

1. Clear the CMD1 bit of the TFCR to 0

to set channels 3 and 4 for normal operation

Complementary PWM mode

Clear complementary

PWM mode

Halt Count

2. Wait at least 1 clock after setting channels 3 and 4

for normal operation and then clear the STR3 and

STR4 bits of the TSTR to 0 to halt the TCNT3 and

TCNT4 counters

Normal operation

Figure 10.69 Clearing the Complementary PWM Mode

10.6.14

ITU Operating Modes

Tables 10.18–10.22 show the ITU operating modes for channels 0–4.

10.6.15

Note on Counter Clearing by Input Capture

If TCNT is cleared (to H'0000) by input capture when its value is H'FFFF, overflow will not

occur.

SH7021 Datasheet(PDF) 311 Page - Renesas Technology Corp