R8CSLASH15 datasheet(102/277 Pages) RENESAS

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R8C/14 Group, R8C/15 Group

13. Timers

Rev.2.10

Jan 19, 2006

Page 90 of 253

REJ09B0164-0210

13.1.3

Event Counter Mode

Event counter mode is mode to count an external signal which inputs from the INT1/CNTR0 pin (See

Table 13.4 Specification of Event Counter Mode). Figure 13.6 shows TXMR Register in Event

Counter Mode.

Table 13.4

Specification of Event Counter Mode

Item

Specification

Count Source

External signal which is input to CNTR0 pin (Active edge is selectable by

software)

Count Operation

• Decrement

• When the timer underflows, the contents in the reload register is reloaded and

the count is inherited

Divide Ratio

1/(n+1)(m+1) n: setting value of PREX register, m: setting value of TX register

Count Start Condition

Write “1” (count starts) to the TXS bit in the TXMR register

Count Stop Condition

Write “0” (count stops) to the TXS bit in the TXMR register

Interrupt Request

Generation Timing

• When Timer X underflows [Timer X interrupt]

INT10/CNTR00,

INT11/CNTR01 Pin

Function

Count source input (INT1 interrupt input)

CNTR0 Pin Function

Programmable I/O port

Read from Timer

The count value can be read by reading the TX and PREX registers.

Write to Timer

• When writing to the TX and PREX registers while the count stops, the value is

written to both the reload register and counter.

• When writing to the TX and PREX registers during the count, the value is written

to each reload register of the TX and PREX registers at the following count

source input and the data is transferred to the counter at the second count

source input and the count re-starts at the third count source input.

Select Function

•INT1/CNTR0 signal polarity switch function

The R0EDG bit can select the active edge of the count source.

• Count source input pin select function

The CNTRSEL bit in the UCON register can select the CNTR00 or CNTR01 pin

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