R8CSLASH15 datasheet(131/277 Pages) RENESAS

131 / 277 page

R8C/14 Group, R8C/15 Group

13. Timers

Rev.2.10

Jan 19, 2006

Page 119 of 253

REJ09B0164-0210

Figure 13.28

TCC1 Register

Timer C Control Register 1

Symbol

Address

After Reset

TCC1

009Bh

00h

Bit Symbol

Bit Name

Function

INT3

_____

Filter Select Bit(1)

NOTES :

When the TCC00 bit in the TCC0 register is set to “0” (count stops), rew rite the TCC13 bit.

When the TCC13 bit is set to “0” (input capture mode), set the TCC12, TCC14 to TCC17 bits to “0”.

TCC17

TCC16

Compare 1 Output Mode Select

Bit(3)

b7 b6

0 0 : CMP output remains unchanged even

w hen compare 1 matches

0 1 : CMP output is reversed w hen compare 1

signal matches

1 0 : CMP output is set to “L” w hen compare 1

signal matches

1 1 : CMP output is set to “H” w hen compare 1

signal matches

When the same value from the INT3

_____

pin is sampled three times continuously, the input is determined.

b3 b2

0 : No reload

1 : Set TC register to “0000h” w hen compare 1

is matched

b1 b0

TCC11

b7 b6 b5 b4

TCC15

TCC10

TCC13

Compare 0 / Capture Select

Bit(2)

TCC12

TCC14

Timer C Counter Reload Select

Bit(3)

Compare 0 Output Mode Select

Bit(3)

b5 b4

0 0 : CMP output remains unchanged even

w hen compare 0 matches

0 1 : CMP output is reversed w hen compare 0

signal matches

1 0 : CMP output is set to “L” w hen compare 0

signal matches

1 1 : CMP output is set to “H” w hen compare 0

signal matches

b1 b0

0 0 : No filter

0 1 : Filter w ith f1 sampling

1 0 : Filter w ith f8 sampling

1 1 : Filter w ith f32 sampling

0 : Select capture (input capture mode)(3)

1 : Select compare 0 output

(output compare mode)

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