R8CSLASH15 datasheet(135/277 Pages) RENESAS

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R8C/14 Group, R8C/15 Group

13. Timers

Rev.2.10

Jan 19, 2006

Page 123 of 253

REJ09B0164-0210

13.3.2

Output Compare Mode

Output compare mode is mode to generate an interrupt request when the value of the TC register

matches the value of the TM0 or TM1 register. Table 13.12 shows Specification of Output Compare

Mode. Figure 13.31 shows an Operating Example in Output Compare Mode.

NOTES:

1. When the corresponding port data is “1”, the waveform is output depending on the setting of the

registers TCC1 and TCOUT. When the corresponding port data is “0”, the fixed level is output (refer

to Figure 13.25 Block Diagram of CMP Waveform Output Unit).

2. Access the TC, TM0, and TM1 registers in 16-bit units.

Table 13.12

Specification of Output Compare Mode

Item

Specification

Count Source

f1, f8, f32, fRING-fast

Count Operation

• Increment

• The value in the TC register is set to “0000h” when a count stops

Count Start Condition

The TCC00 bit in the TCC0 register is set to “1” (count starts)

Counter Stop Condition

The TCC00 bit in the TCC0 register is set to “0” (count stops)

Waveform Output Start

Condition

The TCOUT0 to TCOUT5 bits in the TCOUT register is set to “1” (enables

CMP output).(2)

Waveform Output Stop

Condition

The TCOUT0 to TCOUT5 bits in the TCOUT register is set to “0” (disables

CMP output).

Interrupt Request

Generation Timing

• When a match occurs in the compare circuit 0 [compare 0 interrupt]

• When a match occurs in the compare circuit 1 [compare 1 interrupt]

• When Time C overflows [Timer C interrupt]

INT3/TCIN Pin Function

Programmable I/O port or INT3 interrupt input

P1_0 to P1_2 Pins and

P3_0 to P3_2 Pins

Function

Programmable I/O port or CMP output(1)

Counter Value Reset

Timing

When the TCC00 bit in the TCC0 register is set to “0” (count stops)

Read from Timer(1)

• The value in the compare register can be read out by reading the TM0 and

TM1 registers.

• The count value can be read out by reading the TC register.

Write to Timer(1)

• Write to the TC register is disabled.

• The values written to the TM0 and TM1 registers are stored in the compare

- When the TM0 and TM1 registers are written if the TCC00 bit is set to “0”

(count stops)

- When the counter overflows if the TCC00 bit is set to “1” (during

counting) and the TCC12 bit in the TCC1 register is set to “0” (free-run)

- When the compare 1 matches a counter if the TCC00 bit is set to “1” and

the TCC12 bit is set to “1” (set the TC register to “0000h” when the

compare 1 matches)

Select Function

• Timer C counter reload select function

The TCC12 bit in the TCC1 register can select whether the counter value

in the TC register is set to “0000h” when the compare circuit 1 matches or

not.

• The TCC14 to TCC15 bits in the TCC1 register can select the output level

when the compare circuit 0 matches. The TCC16 to TCC17 bits in the

TCC1 register can select the output level when the compare circuit 1

matches.

• The TCOUT6 to TCOUT7 bits in the TCOUT register can select whether

the output is reversed or not.

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