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R8C/15 Datasheet(PDF) 139 Page - Renesas Technology Corp |
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R8C/15 Datasheet(HTML) 139 Page - Renesas Technology Corp |
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139 / 277 page ![]() R8C/14 Group, R8C/15 Group 14. Serial Interface Rev.2.10 Jan 19, 2006 Page 127 of 253 REJ09B0164-0210 Figure 14.3 U0TB, U0RB and U0BRG Registers UART0 Receive Buffer Register (1) Symbol Address After Reset U0RB 00A7h-00A6h Indeterminate RW NOTES : 1. 2. Nothing is assigned. When w rite, set to “0”. When read, its content is indeterminate. — (b11-b9) — — (b7-b0) — — (b8) — Function Receive data (D7 to D0) RO Receive data (D8) RO b0 b7 (b15) b7 (b8) b0 Bit Symbol Bit Name OER Overrun Error Flag(2) 0 : No overrun error 1 : Overrun error RO RO FER Framing Error Flag(2) 0 : No framing error 1 : Framing error RO PER Parity Error Flag(2) 0 : No parity error 1 : Parity error Read out the UiRB register in 16-bit unit. The SUM, PER, FER and OER bits are set to “0” (no error) w hen the SMD2 to SMD0 bits in the UiMR register are set to “000b” (serial interface disabled) or the RE bit in the U0C1 register is set to “0” (receive disable). The SUM bit is set to “0” (no error) w hen the PER, FER and OER bits are set to “0” (no error). The PER and FER bits are set to “0” even w hen the higher byte of the U0RB register is read out. RO SUM Error Sum Flag(2) 0 : No error 1 : Error UART0 Transmit Buffer Register (1, 2) Symbol Address After Reset U0TB 00A3h-00A2h Indeterminate RW NOTES : 1. 2. (b15) b7 (b8) b0 b0 b7 When the transfer data length is 9-bit long, w rite to high-byte data first then low -byte data. Use the MOV instruction to w rite to this register. Function WO — — (b8-b0) — (b15-b9) Transmit data Nothing is assigned. When w rite, set to “0”. When read, its content is indeterminate. UART0 Bit Rate Register (1, 2, 3) Symbol Address After Reset U0BRG 00A1h Indeterminate Setting Range RW NOTES : 1. 2. 3. b0 Use the MOV instruction to w rite to this register. WO Write to this register w hile the serial I/O is neither transmitting nor receiving. 00h to FFh Function Assuming that set value is n, U0BRG divides the count source by n+1 After setting the CLK0 to CLK1 bits of the U0C0 register, w rite to the U0BRG register. b7 |
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