R8CSLASH15 datasheet(140/277 Pages) RENESAS

140 / 277 page

R8C/14 Group, R8C/15 Group

14. Serial Interface

Rev.2.10

Jan 19, 2006

Page 128 of 253

REJ09B0164-0210

Figure 14.4

U0MR and U0C0 Registers

UART0 Transmit / Receive Mode Register

Symbol

Address

After Reset

U0MR

00A0h

00h

Bit Symbol

Bit Name

Function

NOTES :

Internal / External Clock Select

Bit

0 : Internal clock

1 : External clock(1)

Stop Bit Length Select Bit

—

(b7)

Reserved Bit

Odd / Even Parity Select Bit

Enables w hen PRYE = 1

0 : Odd parity

1 : Even parity

PRYE

Parity Enable Bit

0 : Parity disabled

1 : Parity enabled

Set to “0”

Set the PD1_6 bit in the PD1 register to “0” (input).

SMD2

STPS

0 : 1 Stop Bit

1 : 2 Stop Bits

CKDIR

PRY

Serial Interface Mode Select Bit b2 b1 b0

0 0 0 : Serial interface disabled

0 0 1 : Clock synchronous serial I/O mode

1 0 0 : UART mode transfer data 7 bits long

1 0 1 : UART mode transfer data 8 bits long

1 1 0 : UART mode transfer data 9 bits long

Other than above : Do not set

SMD1

b7 b6 b5 b4

b3 b2 b1 b0

SMD0

UART0 Transmit / Receive Control Register 0

Symbol

Address

After Reset

U0C0

00A4h

08h

Bit Symbol

Bit Name

Function

NOTES :

Nothing is assigned. When w rite, set to “0”.

When read, its content is “0”.

Data Output Select Bit

0 : TXD0 pin is a pin of CMOS output

1 : TXD0 pin is a pin of N-channel open drain output

UFORM

Transfer Format Select Bit 0 : LSB first

1 : MSB first

Reserved Bit

CLK Polarity Select Bit

0 : Transmit data is output at falling edge of transfer

clock and receive data is input at rising edge

1 : Transmit data is output at rising edge of transfer

clock and receive data is input at falling edge

Set to “0”

Transmit Register Empty

Flag

0 : Data in transmit register (during transmit)

1 : No data in transmit register (transmit completed)

CLK1

BRG Count Source Select

Bit(1)

b1 b0

0 0 : Selects f1

0 1 : Selects f8

1 0 : Selects f32

1 1 : Do not set

NCH

CKPOL

—

(b2)

—

(b4)

—

b7 b6 b5 b4

If the BRG count source is sw itched, set the U0BRG register again.

b3 b2

TXEPT

b1 b0

CLK0

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