R8CSLASH15 datasheet(143/277 Pages) RENESAS

143 / 277 page

R8C/14 Group, R8C/15 Group

14. Serial Interface

Rev.2.10

Jan 19, 2006

Page 131 of 253

REJ09B0164-0210

NOTES:

1. Set bits which are not in this table to “0” when writing to the registers in clock synchronous serial I/O

mode.

Table 14.3 lists the I/O Pin Functions in Clock Synchronous Serial I/O Mode. The TXD0 pin outputs “H”

level between the operating mode selection of UART0 and transfer start, an “H” (If the NCH bit is set to

“1” (the N-channel open-drain output), this pin is in a high-impedance state.)

Table 14.2

Registers to Be Used and Settings in Clock Synchronous Serial I/O Mode(1)

Bit

Function

U0TB

0 to 7

Set transmit data

U0RB

0 to 7

Receive data can be read

OER

Overrun error flag

U0BRG

0 to 7

Set bit rate

U0MR

SMD2 to SMD0

Set to “001b”

CKDIR

Select the internal clock or external clock

U0C0

CLK1 to CLK0

Select the count source in the U0BRG register

TXEPT

Transmit register empty flag

NCH

Select TXD0 pin output mode

CKPOL

Select the transfer clock polarity

UFORM

Select the LSB first or MSB first

U0C1

Set this bit to “1” to enable transmit/receive

Transmit buffer empty flag

Set this bit to “1” to enable reception

Reception complete flag

UCON

U0IRS

Select the factor of UART0 transmit interrupt

U0RRM

Set this bit to “1” to use continuous receive mode

CNTRSEL

Set this bit to “1” to select P1_5/RXD0/CNTR01/INT11

Table 14.3

I/O Pin Functions in Clock Synchronous Serial I/O Mode

Pin Name

Function

Selection Method

TXD0(P1_4)

Output serial data

(Outputs dummy data when performing receive only)

RXD0(P1_5)

Input serial data

PD1_5 bit in PD1 register=0

(P1_5 can be used as an input port when performing transmit

only)

CLK0(P1_6)

Output transfer clock

CKDIR bit in U0MR register=0

Input transfer clock

CKDIR bit in U0MR register=1

PD1_6 bit in PD1 register=0

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