R8CSLASH15 datasheet(271/277 Pages) RENESAS

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REVISION HISTORY

R8C/14 Group, R8C/15 Group Hardware

2.00

Jan 12, 2006

Table 6.2 Setting Procedure of Voltage Monitor 1 Reset Associated Bit

revised

Table 6.3 Setting Procedure of Voltage Monitor 2 Interrupt and Voltage

Monitor 2 Reset Associated Bit revised

Table 8.2 Bus Cycles for Access Space of the R8C/15 Group added,

Table 8.3 Access Unit and Bus Operation;

“SFR”

→ “SFR, Data flash”,

“ROM/RAM”

→ “ROM (Program ROM), RAM” revised

Table 9.1 Specification of Clock Generation Circuit NOTE2 deleted

Figure 9.1 Clock Generation Circuit revised

Figure 9.2 CM0 Register NOTE2 revised

Figure 9.4 OCD Register NOTES 3, 4 revised

Figure 9.5 HRA0 Register NOTE2 revised

9.1 Main Clock;

“After reset, ...”

→ “During reset and after reset, ...” revised

9.2.1 Low-Speed On-Chip Oscillator Clock;

“The application ... to accommodate the frequency range.”

→

“The application ... for the frequency change.”

9.3.2 CPU Clock;

“When changing the clock source ... the OCD2 bit.” deleted

9.4.1 Normal Operating Mode;

“... into three modes”

→ “... into four modes” revised

Table 9.2 Setting and Mode of Clock Associated Bit revised

9.4.1.1 High-Speed Mode, 9.4.1.2 Medium-Speed Mode;

“Set the CM06 bit to “1” ... on-chip oscillator mode.” deleted

9.4.1.3 High-Speed, Low-Speed On-Chip Oscillator Mode;

“9.4.1.3 On-Chip Oscillator Mode”

→ “9.4.1.3 High-Speed, Low-Speed

On-Chip Oscillator Mode” revised,

“Set the CM06 bit to “1” ... high-speed and medium-speed.” deleted

Figure 9.8 State Transition to Stop and Wait Modes;

“Figure 9.8 State Transition to Stop and Wait Modes”

→ “Figure 9.8

State Transition of Power Control” revised

Figure 9.9 State Transition in Normal Operating Mode deleted

9.5.1 How to Use Oscillation Stop Detection Function;

“

• This function cannot ... is 2 MHz or below. ...” →

“

• This function cannot ... is below 2 MHz. ...” revised

Figure 9.9 Procedure of Switching Clock Source From Low-Speed On-

Chip Oscillator to Main Clock revised

Figure 10.1 PRCR Register “00XXX000b”

→ ”00h” revised

Figure 11.10 Judgement Circuit of Interrupts Priority Level NOTE1 deleted

Figure 11.11 INTEN and INT0F Registers;

INT0F Register “XXXXX000b”

→ ”00h” revised

Rev.

Date

Description

Page

Summary

R8C/15 Datasheet(PDF) 271 Page - Renesas Technology Corp

R8C/15 Datasheet(HTML) 271 Page - Renesas Technology Corp

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