R8CSLASH15 datasheet(273/277 Pages) RENESAS

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C - 8

REVISION HISTORY

R8C/14 Group, R8C/15 Group Hardware

2.00

Jan 12, 2006

103

Table 13.7 Specification of Timer Mode;

“

• When writing ... registers (the data is transferred to the counter

when the following count source is input) while the TZWC bit is set to

“0” (writing to the reload register and counter simultaneously).”

→

“

• When writing ... registers at the following count source input and the

data is transferred to the counter at the second count source input and

the count re-starts at the third count source input.” revised

108, 112 Table 13.9 Specification of Programmable One-Shot Generation Mode,

Table 13.10

Specification of Programmable Wait One-Shot Generation

Mode Specifications;

Count Operation; “

• When a count completes, ...” → “• When a count

stops, ...” revised

112

Table 13.10

Specification of Programmable Wait One-Shot Generation

Mode Specifications;

NOTE1, 2, 3 revised

116

Figure 13.25 Block Diagram of CMP Waveform Output Unit revised

123

Table 13.12 Specification of Output Compare Mode NOTE1 revised

124

Figure 13.31 Operating Example of Timer C in Output Compare Mode

revised

127

Figure 14.3 U0TB, U0RB and U0BRG Registers;

U0TB and U0RB Registers revised, U0BRG Register NOTE3 added

128

Figure 14.4 U0MR and U0C0 Registers;

U0C0 Register NOTE1 added

136

Table 14.5 Registers to Be Used and Settings in UART Mode;

U0BRG: “

−“ → “0 to 7” revised

169

Figure 16.1 Block Diagram of A/D Converter “Vref“

→ “Vcom” revised

170, 173,

175

Figure 16.2 ADCON0 and ADCON1 Registers,

Figure 16.4 ADCON0 and ADCON1 Registers in One-Shot Mode,

Figure 16.5 ADCON0 and ADCON1 Registers in Repeat Mode;

ADCON0 Register revised

176 to

178

Figure 16.6 Timing Diagram of A/D Conversion revised and

16.4 A/D Conversion Cycles to 16.6 Inflow Current Bypass Circuit added

180, 181 Figure 17.1 Configuration of Programmable I/O Ports (1),

Figure 17.2 Configuration of Programmable I/O Ports (2); NOTE1 added

182

Figure 17.3 Configuration of Programmable I/O Ports (3) NOTE4 added

184

Figure 17.5 PD1, PD3 and PD4 Registers,

Figure 17.6 P1, P3 and P4 Registers; NOTE1, 2 revised

185

Figure 17.7 PUR0 and PUR1 Registers revised

186 to

189

17.4 Port setting added, Table 17.4 Port P1_0/KI0/AN8/CMP0_0 Setting

to Table 17.17 Port P4_5/INT0 Setting added

191

Table 18.1 Flash Memory Version Performance;

Program and Erase Endurance: (Program area)

→ (Program ROM),

(Data area)

→ (Data flash) revised

Rev.

Date

Description

Page

Summary

R8C/15 Datasheet(PDF) 273 Page - Renesas Technology Corp

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