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4501 Datasheet(PDF) 152 Page - Renesas Technology Corp

Part # 4501
Description  4-BIT CISC SINGLE-CHIP MICROCOMPUTER 4500 SERIES
PDF  212 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

4501 Datasheet(HTML) 152 Page - Renesas Technology Corp

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2.4 A/D converter
2-35
4501 Group
APPLICATION
Rev.2.01
Feb 07, 2005
REJ09B0192-0201
Fig. 2.4.2 A/D conversion mode setting example
b3b0
➀ Disable Interrupts
A/D interrupt is temporarily disabled.
Interrupt enable flag INTE
Interrupt control register V2
“0”
✕
✕
All interrupts disabled (DI instruction)
A/D interrupt occurrence disabled
(TV2A instruction)
0
✕
➁ Set A/D Converter
A/D conversion mode is selected to A/D operation mode.
Analog input pin AIN0 is selected.
A/D control register Q1
A/D conversion mode, AIN0 selected
(TQ1A instruction)
b3b0
✕
0
0 0
➂ Clear Interrupt Request
A/D interrupt activated condition is cleared.
A/D conversion completion flag ADF “0”
A/D conversion interrupt activated condition cleared
(SNZAD instruction)
Note when the interrupt request is cleared
When ➂ is executed, considering the skip of the next instruction according to the
flag ADF, insert the NOP instruction after the SNZAD instruction.
When interrupt is
not used
When interrupt is used
➃ Set Interrupt
Interrupts except A/D conversion is
enabled (EI instruction)
➃ Set Interrupt
A/D conversion interrupt temporarily disabled is enabled.
b3
b0
1
✕✕ ✕
Interrupt control register V2
A/D interrupt occurrence enabled
(TV2A instruction)
Interrupt enable flag INTE
“1”
All interrupts enabled
(EI instruction)
➄ Start A/D Conversion
A/D conversion operation is started (ADST instruction).
When interrupt is not used
When interrupt is used
➅ Check A/D Interrupt Request
A/D conversion completion flag is
checked (SNZAD instruciton)
➅ A/D Conversion Interrupt Occur
➆ Execute A/D Conversion
High-order 8 bits of register AD
→ Register A and register B (TABAD instruction)
Low-order 2 bits of register AD
→ High-order 2 bits of register A (TALA instruction)
“0” is set to low-order 2 bits of register A
“✕”: it can be “0” or “1.”
When A/D conversion is executed by the same channel, ➄ to ➆ is repeated.
When A/D conversion is executed by the another channel, ➀ to ➆ is repeated.



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