TMS320VC5504 datasheet(104/128 Pages) TI

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TMS320VC5504

Fixed-Point Digital Signal Processor

SPRS609A – JUNE 2009 – REVISED JULY 2009

www.ti.com

Table 6-31. Timing Requirements for I2S [I/O = 1.8 V](1) (see Figure 6-25)

MASTER

SLAVE

NO.

CVDD = 1.05 V

CVDD = 1.3 V

CVDD = 1.05 V

CVDD = 1.3 V

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

50 or

40 or

50 or

40 or

tc(CLK)

Cycle time, I2S_CLK

2P(1)(2)

tw(CLKH)

Pulse duration, I2S_CLK high

tw(CLKL)

Pulse duration, I2S_CLK low

Setup time, I2S_RX valid before

tsu(RXV-CLKH)

I2S CLK high (CLKPOL = 0)

Setup time, I2S_RX valid before

tsu(RXV-CLKL)

I2S_CLK low (CLKPOL = 1)

Hold time, I2S_RX valid after

th(CLKH-RXV)

I2S_CLK high (CLKPOL = 0)

Hold time, I2S_RX valid after

th(CLKL-RXV)

I2S_CLK low (CLKPOL = 1)

Setup time, I2S_FS valid before

tsu(FSV-CLKH)

–

I2S_CLK high (CLKPOL = 0)

Setup time, I2S_FS valid before

tsu(FSV-CLKL)

–

I2S_CLK low (CLKPOL = 1)

Hold time, I2S_FS valid after

tw(CLKH) +

th(CLKH-FSV)

–

I2S_CLK high (CLKPOL = 0)

0.6(3)

Hold time, I2S_FS valid after

tw(CLKL) +

th(CLKL-FSV)

–

I2S_CLK low (CLKPOL = 1)

0.6(3)

(1)

P = SYSCLK period in ns. For example, when running parts at 100 MHz, use P = 10 ns.

(2)

Use whichever value is greater.

(3)

In Slave Mode, I2S_FS is required to be latched on both edges of I2S input clock (I2S_CLK).

Peripheral Information and Electrical Specifications

104

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