TMS320VC5504 datasheet(105/128 Pages) TI

105 / 128 page

TMS320VC5504

Fixed-Point Digital Signal Processor

www.ti.com

SPRS609A – JUNE 2009 – REVISED JULY 2009

Table 6-32. Switching Characteristics Over Recommended Operating Conditions for I2S Output

[I/O = 3.3 V, 2.8 V, or 2.5 V] (see Figure 6-25)

MASTER

SLAVE

PARAMETER

CVDD = 1.05 V

CVDD = 1.3 V

CVDD = 1.05 V

CVDD = 1.3 V

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

40 or

tc(CLK)

Cycle time, I2S_CLK

2P(1)(2)

tw(CLKH)

Pulse duration, I2S_CLK high (CLKPOL = 0)

tw(CLKL)

Pulse duration, I2S_CLK low (CLKPOL = 1)

tw(CLKL)

Pulse duration, I2S_CLK low (CLKPOL = 0)

tw(CLKH)

Pulse duration, I2S_CLK high (CLKPOL = 1)

tdmax(CLKL-

Output Delay time, I2S_CLK low to I2S_DX

DXV)

valid (CLKPOL = 0)

tdmax(CLKH-

Output Delay time, I2S_CLK high to I2S_DX

DXV)

valid (CLKPOL = 1)

Output Hold time, I2S_CLK high to I2S_DX

toh(DXV-CLKH)

invalid (CLKPOL = 0)

toh(DXV-

Output Hold time, I2S_CLK low to I2S_DX

CLKL)

invalid (CLKPOL = 1)

tdmax(CLKL-

Delay time, I2S_CLK low to I2S_FS valid

–

FSV)

(CLKPOL = 0)

tdmax(CLKH-

Delay time, I2S_CLK high to I2S_FS valid

–

FSV)

(CLKPOL = 1)

(1)

P = SYSCLK period in ns. For example, when running parts at 100 MHz, use P = 10 ns.

(2)

Use whichever value is greater.

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