TMS320VC5504 datasheet(108/128 Pages) TI

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6.15.2 SPI Electrical Data/Timing

TMS320VC5504

Fixed-Point Digital Signal Processor

SPRS609A – JUNE 2009 – REVISED JULY 2009

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Table 6-35. Timing Requirements for SPI input (see Figure 6-26 through Figure 6-29)

CVDD = 1.05 V

CVDD = 1.3 V

NO.

UNIT

MIN

MAX

MIN

MAX

66.4 or

40 or

tC(SCLK)

Cycle time, SPI_CLK

4P(1)(2)

tw(SCLKH)

Pulse duration, SPI_CLK high

tw(SCLKL)

Pulse duration, SPI_CLK low

Setup time, SPI_RX valid before SPI_CLK high, SPI Mode 0

Setup time, SPI_RX valid before SPI_CLK low, SPI Mode 1

tsu(SRXV-SCLK)

Setup time, SPI_RX valid before SPI_CLK high, SPI Mode 2

Setup time, SPI_RX valid before SPI_CLK high, SPI Mode 3

Hold time, SPI_RX vaild after SPI_CLK high, SPI Mode 0

Hold time, SPI_RX vaild after SPI_CLK low, SPI Mode 1

th(SCLK-SRXV)

Hold time, SPI_RX vaild after SPI_CLK low, SPI Mode 2

Hold time, SPI_RX vaild after SPI_CLK high, SPI Mode 3

(1)

P = SYSCLK period in ns. For example, when running parts at 100 MHz, use P = 10 ns.

(2)

Use whichever value is greater.

Table 6-36. Switching Characteristics Over Recommended Operating Conditions for SPI Outputs

(see Figure 6-26 through Figure 6-29)

CVDD = 1.05 V

CVDD = 1.3 V

NO.

PARAMETER

UNIT

MIN

MAX

MIN

MAX

Delay time, SPI_CLK low to SPI_TX vaild, SPI

Mode 0

Delay time, SPI_CLK high to SPI_TX vaild, SPI

Mode 1

td(SCLK-STXV)

Delay time, SPI_CLK high to SPI_TX vaild, SPI

Mode 2

Delay time, SPI_CLK low to SPI_TX vaild, SPI

Mode 3

Output hold time, SPI_CLK high to SPI_TX invaild,

tw(SCLKH) -

tw(SCLKH) - 4

SPI Mode 0

4.5

Output hold time, SPI_CLK low to SPI_TX invaild,

tw(SCLKL) -

tw(SCLKL) - 4

SPI Mode 1

4.5

toh(SCLK-STXIV)

Output hold time, SPI_CLK low to SPI_TX invaild,

tw(SCLKL) -

tw(SCLKL) - 4

SPI Mode 2

4.5

Output hold time, SPI_CLK high to SPI_TX invaild,

tw(SCLKH) -

tw(SCLKH) - 4

SPI Mode 3

4.5

td(SPICS-SCLK)

Delay time, SPI_CS active to SPI_CLK active

tC - 8 + D

(1)

tC - 8 + D

(1)

Output hold time, SPI_CS inactive to SPI_CLK

toh(SCLKI-SPICSI)

0.5tC - 2

inactive

(1)

D is the programable data delay in ns. Data delay can be programmed to 0, 1, 2, or 3 SPICLK clock cycles.

Peripheral Information and Electrical Specifications

108

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