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TMS320VC5504 Datasheet(PDF) 112 Page - Texas Instruments |
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TMS320VC5504 Datasheet(HTML) 112 Page - Texas Instruments |
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112 / 128 page  TMS320VC5504 Fixed-Point Digital Signal Processor SPRS609A – JUNE 2009 – REVISED JULY 2009 www.ti.com Table 6-37. Universal Serial Bus (USB) Registers (continued) CPU WORD ACRONYM REGISTER DESCRIPTION ADDRESS 8424h FIFO1R1 Transmit and Receive FIFO Register 1 for Endpoint 1 8425h FIFO1R2 Transmit and Receive FIFO Register 2 for Endpoint 1 8428h FIFO2R1 Transmit and Receive FIFO Register 1 for Endpoint 2 8429h FIFO2R2 Transmit and Receive FIFO Register 2 for Endpoint 2 842Ch FIFO3R1 Transmit and Receive FIFO Register 1 for Endpoint 3 842Dh FIFO3R2 Transmit and Receive FIFO Register 2 for Endpoint 3 8430h FIFO4R1 Transmit and Receive FIFO Register 1 for Endpoint 4 8431h FIFO4R2 Transmit and Receive FIFO Register 2 for Endpoint 4 Dynamic FIFO Control Registers 8460h - Reserved 8461h Transmit Endpoint FIFO Size, Receive Endpoint FIFO Size (Index register set to TXFIFOSZ_RXFIFOSZ select Endpoints 1-4) 8464h TXFIFOADDR Transmit Endpoint FIFO Address (Index register set to select Endpoints 1-4) 8465h RXFIFOADDR Receive Endpoint FIFO Address (Index register set to select Endpoints 1-4) 846Ch - Reserved Control and Status Register for Endpoint 0 8500h - Reserved 8501h PERI_CSR0 Control Status Register for Peripheral Endpoint 0 8504h - Reserved 8505h - Reserved 8508h COUNT0 Number of Received Bytes in Endpoint 0 FIFO 8509h - Reserved 850Ch - Reserved CONFIGDATA Returns details of core configuration. 850Dh (Upper byte of 850Dh) Control and Status Register for Endpoint 1 8510h TXMAXP Maximum Packet Size for Peripheral/Host Transmit Endpoint 8511h PERI_TXCSR Control Status Register for Peripheral Transmit Endpoint (peripheral mode) 8514h RXMAXP Maximum Packet Size for Peripheral/Host Receive Endpoint 8515h PERI_RXCSR Control Status Register for Peripheral Receive Endpoint (peripheral mode) 8518h RXCOUNT Number of Bytes in the Receiving Endpoint's FIFO 8519h - Reserved 851Ch - Reserved 851Dh - Reserved Control and Status Register for Endpoint 2 8520h TXMAXP Maximum Packet Size for Peripheral/Host Transmit Endpoint 8521h PERI_TXCSR Control Status Register for Peripheral Transmit Endpoint (peripheral mode) 8524h RXMAXP Maximum Packet Size for Peripheral/Host Receive Endpoint 8525h PERI_RXCSR Control Status Register for Peripheral Receive Endpoint (peripheral mode) 8528h RXCOUNT Number of Bytes in Host Receive endpoint FIFO 8529h - Reserved 852Ch - Reserved 852Dh - Reserved Control and Status Register for Endpoint 3 8530h TXMAXP Maximum Packet Size for Peripheral/Host Transmit Endpoint 8531h PERI_TXCSR Control Status Register for Peripheral Transmit Endpoint (peripheral mode) 8534h RXMAXP Maximum Packet Size for Peripheral/Host Receive Endpoint Peripheral Information and Electrical Specifications 112 Submit Documentation Feedback |
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