TMS320VC5504 datasheet(114/128 Pages) TI

114 / 128 page

TMS320VC5504

Fixed-Point Digital Signal Processor

SPRS609A – JUNE 2009 – REVISED JULY 2009

www.ti.com

Table 6-37. Universal Serial Bus (USB) Registers (continued)

CPU WORD

ACRONYM

ADDRESS

9869h

RXGCR2[3]

Receive Channel 3 Global Configuration Register 2

986Ch

RXHPCR1A[3]

Receive Channel 3 Host Packet Configuration Register 1 A

986Dh

RXHPCR2A[3]

Receive Channel 3 Host Packet Configuration Register 2 A

9870h

RXHPCR1B[3]

Receive Channel 3 Host Packet Configuration Register 1 B

9871h

RXHPCR2B[3]

Receive Channel 3 Host Packet Configuration Register 2 B

A000h

DMA_SCHED_CTRL1

CDMA Scheduler Control Register 1

A001h

DMA_SCHED_CTRL2

CDMA Scheduler Control Register 1

A800h + 4

× N

ENTRYLSW[N]

CDMA Scheduler Table Word N Registers LSW (N = 0 to 63)

A801h + 4

× N

ENTRYMSW[N]

CDMA Scheduler Table Word N Registers MSW (N = 0 to 63)

Queue Manager (QMGR) Registers

C000h

Reserved

C001h

Reserved

C008h

DIVERSION1

Queue Manager Queue Diversion Register 1

C009h

DIVERSION2

Queue Manager Queue Diversion Register 2

C020h

FDBSC0

Queue Manager Free Descriptor/Buffer Starvation Count Register 0

C021h

FDBSC1

Queue Manager Free Descriptor/Buffer Starvation Count Register 1

C024h

FDBSC2

Queue Manager Free Descriptor/Buffer Starvation Count Register 2

C025h

FDBSC3

Queue Manager Free Descriptor/Buffer Starvation Count Register 3

C028h

FDBSC4

Queue Manager Free Descriptor/Buffer Starvation Count Register 4

C029h

FDBSC5

Queue Manager Free Descriptor/Buffer Starvation Count Register 5

C02Ch

FDBSC6

Queue Manager Free Descriptor/Buffer Starvation Count Register 6

C02Dh

FDBSC7

Queue Manager Free Descriptor/Buffer Starvation Count Register 7

C080h

LRAM0BASE1

Queue Manager Linking RAM Region 0 Base Address Register 1

C081h

LRAM0BASE2

Queue Manager Linking RAM Region 0 Base Address Register 2

C084h

LRAM0SIZE

Queue Manager Linking RAM Region 0 Size Register

C085h

Reserved

C088h

LRAM1BASE1

Queue Manager Linking RAM Region 1 Base Address Register 1

C089h

LRAM1BASE2

Queue Manager Linking RAM Region 1 Base Address Register 2

C090h

PEND0

Queue Manager Queue Pending 0

C091h

PEND1

Queue Manager Queue Pending 1

C094h

PEND2

Queue Manager Queue Pending 2

C095h

PEND3

Queue Manager Queue Pending 3

C098h

PEND4

Queue Manager Queue Pending 4

C099h

PEND5

Queue Manager Queue Pending 5

D000h + 16

× R

QMEMRBASE1[R]

Queue Manager Memory Region R Base Address Register 1 (R = 0 to 15)

D001h + 16

× R

QMEMRBASE2[R]

Queue Manager Memory Region R Base Address Register 2 (R = 0 to 15)

D004h + 16

× R

QMEMRCTRL1[R]

Queue Manager Memory Region R Control Register (R = 0 to 15)

D005h + 16

× R

QMEMRCTRL2[R]

Queue Manager Memory Region R Control Register (R = 0 to 15)

E000h + 16

× N

CTRL1A

Queue Manager Queue N Control Register 1A (N = 0 to 63)

E001h + 16

× N

CTRL2A

Queue Manager Queue N Control Register 2A (N = 0 to 63)

E004h + 16

× N

CTRL1B

Queue Manager Queue N Control Register 1B (N = 0 to 63)

E005h + 16

× N

CTRL2B

Queue Manager Queue N Control Register 2B (N = 0 to 63)

E008h + 16

× N

CTRL1C

Queue Manager Queue N Control Register 1C (N = 0 to 63)

E009h + 16

× N

CTRL2C

Queue Manager Queue N Control Register 2C (N = 0 to 63)

E00Ch + 16

× N

CTRL1D

Queue Manager Queue N Control Register 1D (N = 0 to 63)

E00Dh + 16

× N

CTRL2D

Queue Manager Queue N Control Register 2D (N = 0 to 63)

Peripheral Information and Electrical Specifications

114

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