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TMS320VC5504 Datasheet(PDF) 113 Page - Texas Instruments |
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TMS320VC5504 Datasheet(HTML) 113 Page - Texas Instruments |
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113 / 128 page  TMS320VC5504 Fixed-Point Digital Signal Processor www.ti.com SPRS609A – JUNE 2009 – REVISED JULY 2009 Table 6-37. Universal Serial Bus (USB) Registers (continued) CPU WORD ACRONYM REGISTER DESCRIPTION ADDRESS 8535h PERI_RXCSR Control Status Register for Peripheral Receive Endpoint (peripheral mode) 8538h RXCOUNT Number of Bytes in Host Receive endpoint FIFO 8539h - Reserved 853Ch - Reserved 853Dh - Reserved Control and Status Register for Endpoint 4 8540h TXMAXP Maximum Packet Size for Peripheral/Host Transmit Endpoint 8541h PERI_TXCSR Control Status Register for Peripheral Transmit Endpoint (peripheral mode) 8544h RXMAXP Maximum Packet Size for Peripheral/Host Receive Endpoint 8545h PERI_RXCSR Control Status Register for Peripheral Receive Endpoint (peripheral mode) 8548h RXCOUNT Number of Bytes in Host Receive endpoint FIFO 8549h - Reserved 854Ch - Reserved 854Dh - Reserved CPPI DMA (CMDA) Registers 9000h - Reserved 9001h - Reserved 9004h TDFDQ CDMA Teardown Free Descriptor Queue Control Register 9008h DMAEMU CDMA Emulation Control Register 9800h TXGCR1[0] Transmit Channel 0 Global Configuration Register 1 9801h TXGCR2[0] Transmit Channel 0 Global Configuration Register 2 9808h RXGCR1[0] Receive Channel 0 Global Configuration Register 1 9809h RXGCR2[0] Receive Channel 0 Global Configuration Register 2 980Ch RXHPCR1A[0] Receive Channel 0 Host Packet Configuration Register 1 A 980Dh RXHPCR2A[0] Receive Channel 0 Host Packet Configuration Register 2 A 9810h RXHPCR1B[0] Receive Channel 0 Host Packet Configuration Register 1 B 9811h RXHPCR2B[0] Receive Channel 0 Host Packet Configuration Register 2 B 9820h TXGCR1[1] Transmit Channel 1 Global Configuration Register 1 9821h TXGCR2[1] Transmit Channel 1 Global Configuration Register 2 9828h RXGCR1[1] Receive Channel 1 Global Configuration Register 1 9829h RXGCR2[1] Receive Channel 1 Global Configuration Register 2 982Ch RXHPCR1A[1] Receive Channel 1 Host Packet Configuration Register 1 A 982Dh RXHPCR2A[1] Receive Channel 1 Host Packet Configuration Register 2 A 9830h RXHPCR1B[1] Receive Channel 1 Host Packet Configuration Register 1 B 9831h RXHPCR2B[1] Receive Channel 1 Host Packet Configuration Register 2 B 9840h TXGCR1[2] Transmit Channel 2 Global Configuration Register 1 9841h TXGCR2[2] Transmit Channel 2 Global Configuration Register 2 9848h RXGCR1[2] Receive Channel 2 Global Configuration Register 1 9849h RXGCR2[2] Receive Channel 2 Global Configuration Register 2 984Ch RXHPCR1A[2] Receive Channel 2 Host Packet Configuration Register 1 A 984Dh RXHPCR2A[2] Receive Channel 2 Host Packet Configuration Register 2 A 9850h RXHPCR1B[2] Receive Channel 2 Host Packet Configuration Register 1 B 9851h RXHPCR2B[2] Receive Channel 2 Host Packet Configuration Register 2 B 9860h TXGCR1[3] Transmit Channel 3 Global Configuration Register 1 9861h TXGCR2[3] Transmit Channel 3 Global Configuration Register 2 9868h RXGCR1[3] Receive Channel 3 Global Configuration Register 1 Submit Documentation Feedback Peripheral Information and Electrical Specifications 113 |
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