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TMS320VC5504 Datasheet(PDF) 111 Page - Texas Instruments |
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TMS320VC5504 Datasheet(HTML) 111 Page - Texas Instruments |
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111 / 128 page  TMS320VC5504 Fixed-Point Digital Signal Processor www.ti.com SPRS609A – JUNE 2009 – REVISED JULY 2009 Table 6-37. Universal Serial Bus (USB) Registers (continued) CPU WORD ACRONYM REGISTER DESCRIPTION ADDRESS 8030h INTMSKSETR1 USB Interrupt Mask Set Register 1 8031h INTMSKSETR2 USB Interrupt Mask Set Register 2 8034h INTMSKCLRR1 USB Interrupt Mask Clear Register 1 8035h INTMSKCLRR2 USB Interrupt Mask Clear Register 2 8038h INTMASKEDR1 USB Interrupt Source Masked Register 1 8039h INTMASKEDR2 USB Interrupt Source Masked Register 2 803Ch EOIR USB End of Interrupt Register 8040h INTVECTR1 USB Interrupt Vector Register 1 8041h INTVECTR2 USB Interrupt Vector Register 2 8050h GREP1SZR1 Generic RNDIS EP1Size Register 1 8051h GREP1SZR2 Generic RNDIS EP1Size Register 2 8054h GREP2SZR1 Generic RNDIS EP2 Size Register 1 8055h GREP2SZR2 Generic RNDIS EP2 Size Register 2 8058h GREP3SZR1 Generic RNDIS EP3 Size Register 1 8059h GREP3SZR2 Generic RNDIS EP3 Size Register 2 805Ch GREP4SZR1 Generic RNDIS EP4 Size Register 1 805Dh GREP4SZR2 Generic RNDIS EP4 Size Register 2 Common USB Registers 8400h FADDR_POWER Function Address Register, Power Management Register 8401h INTRTX Interrupt Register for Endpoint 0 plus Transmit Endpoints 1 to 4 8404h INTRRX Interrupt Register for Receive Endpoints 1 to 4 8405h INTRTXE Interrupt enable register for INTRTX 8408h INTRRXE Interrupt Enable Register for INTRRX 8409h INTRUSB_INTRUSBE Interrupt Register for Common USB Interrupts, Interrupt Enable Register 840Ch FRAME Frame Number Register 840Dh Index Register for Selecting the Endpoint Status and Control Registers, Register to INDEX_TESTMODE Enable the USB 2.0 Test Modes USB Indexed Registers 8410h Maximum Packet Size for Peripheral/Host Transmit Endpoint. (Index register set to TXMAXP_INDX select Endpoints 1-4) 8411h Control Status Register for Endpoint 0 in Peripheral Mode. (Index register set to PERI_CSR0_INDX select Endpoint 0) Control Status Register for Peripheral Transmit Endpoint. (Index register set to select PERI_TXCSR_INDX Endpoints 1-4) 8414h Maximum Packet Size for Peripheral/Host Receive Endpoint. (Index register set to RXMAXP_INDX select Endpoints 1-4) 8415h Control Status Register for Peripheral Receive Endpoint. (Index register set to select PERI_RXCSR_INDX Endpoints 1-4) 8418h Number of Received Bytes in Endpoint 0 FIFO. (Index register set to select Endpoint COUNT0_INDX 0) Number of Bytes in Host Receive Endpoint FIFO. (Index register set to select RXCOUNT_INDX Endpoints 1- 4) 8419h - Reserved 841Ch - Reserved 841Dh CONFIGDATA_INDC Returns details of core configuration. (index register set to select Endpoint 0) (Upper byte of 841Dh) USB FIFO Registers 8420h FIFO0R1 Transmit and Receive FIFO Register 1 for Endpoint 0 8421h FIFO0R2 Transmit and Receive FIFO Register 2 for Endpoint 0 Submit Documentation Feedback Peripheral Information and Electrical Specifications 111 |
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